The present invention relates generally to a frequency generator for generating a digital signal and, in particular, to a digital clock frequency multiplier that increases the frequency of an input clock signal.
Clock frequency multipliers are widely used in integrated circuits. Conventionally, phase locked loops (PLLs) are used as clock frequency multipliers to increase the frequency of an input clock signal. However, PLLs require much time and design effort to ensure stability, consume large silicon area and often require external components for usage, resulting in increased costs. Additionally, because PLLs have high lock times, the frequency of the input clock signal cannot be changed quickly. Further, PLLs are only suited for handling input clock signals of limited frequency and duty cycle ranges, and individual PLLs have limited multiplication ranges.
In view of the foregoing, it would be desirable to have an inexpensive programmable digital clock frequency multiplier that has low lock time, a wide multiplication range and that is suited for handling a wide range of input frequencies and duty cycles.